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PPI and 3D Package technologies refer to the process developed on an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. It is essentially a wafer scale process technologies, include multilayer, three dimensional interconnection and various termination technology. The completed service can be either ready for next level packaging process, such as wire bond package or a completed chip scale package.

The advantages of the services offers smallest form factor, lesser weight, simplified supply chain, lowest production costs and enhanced product performance through integration with emiconductor process technology such as enhanced high Q inductor. It is widely used in portable devices such as cell phones, tablet, notebook...etc. Furthermore, PPI and 3D package technologies paves the way for true integration of IC process, packaging, testing, and burn-in at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment.

As PPI and 3D package technologies are the extended service of wafer fab processes, highly integrated with device design and bonded to next level package needs, which leads highly customized service nature. PPI and 3D package technologies developed at Xintec includes:

XinPPI-Al or XinPPI-Cu multilayer redistribution process.

  • Al or Gold surface finish to fulfill next level package needs, such as wire bond or solder joint.
  • Lead Free BGA with printing or ball placement process option.
  • Three dimensional IC interconnection (3D IC)
  • Three dimensional I/O redistribution (3D RDL)

XinPPI-TiNiVAg backside metal coating and backside grinding service.

Silicon Interposer with TSV process option.

Tech XinPPI-Cu 3D IC XinPPI on Glass XinPPI-CuNiAu XinPPI-Ti/NiV/Ag
Key Features
  • Cu wiring
  • PBO isolation
  • Lead free BGA
  • Al Wiring
  • Cu TSV
  • Oxide isolation
  • Al wiring
  • Glass substrate
  • Wire Bondable
  • Cu wiring
  • PBO isolation
  • Wire Bond and BGA backend option
  • Ti/Niv/Ag backside metal coating
  • Wafer Thinning

Future Technology

  • Wafer Level Fan In/Out Module to meet 3D stack and heterogeneous package integration needs

Product Applications

  • Integrated Passive Device (IPD)
  • Power Discrete
  • Power Management IC and Analogue IC
  • Cellular Phone RF IC
  • Capacitive Coupler